1. Field of the Invention
The present invention relates to a failure-data storage system which is used for storing failure-data from a test of an IC (Integrated Circuit), such as a memory IC.
This application is based on patent application No. Hei 09-044333 filed in Japan, the content of which is incorporated herein by reference.
2. Description of Related Art
In Memory ICs, speed is increasing and capacity is also increasing as performance improves in devices having memory ICs built in. For example, 64 Mbit memory devices are in mass production and 256 Mbit memory devices are in prototype production. Furthermore, as the capacity of memory ICs increase, multiple data bit memory devices are becoming popular such as 8 bit or 16 bit. In tests of multiple data bit memory devices, an IC tester is equipped with a failure-data storage circuit for storing failure-data for analysis of the failure result.
A higher-performance failure-data storage system is required for testers for memory ICs with large capacity and multiple data bits. Therefore, a control circuit corresponding to the multiple data bit memory device is required for the failure-data storage circuit.
Memory devices are generally used in failure-data storage circuits to store failure-data of memory ICs. FIG. 3 shows a block diagram of a conventional control circuit in which memory device 60 with a 1 bit construction is used. According to FIG. 3, failure-data after a test are synchronized with a timing clock for the memory IC 60, and the resulting signal is input to the memory IC 60 as a write pulse: -WE. At the same time, a write address select signal is input from address select signal generator 54. Failure-data storage system 61 gives a plurality of accesses for the test to the same address of the device under test using a test pattern. In such a case, it is necessary to store the failure-data as accumulated data for each memory IC without erasing the previous data. Consequently, data input from the memory IC 60 is pulled up, and failure-data is input as a signal: -WE in FIG. 3. FIG. 4 is a timing chart representing the transitions of the signals in FIG. 3.
There is a problem in that the conventional failure-data storage system cannot independently control every bit of a multiple data bit device which is used as a failure-data memory. For this reason, failure-data for the same address is overwritten every time the test is done, and accumulated data cannot be stored.